Processor register

Results: 545



#Item
21wgc2_OA_title.fm Page i Thursday, April 20, :25 PM  fro m WRITE GREAT CODE V ol um e 2 : T hi nk in g Low -Lev el , W r i t in g Hi gh -Lev el

wgc2_OA_title.fm Page i Thursday, April 20, :25 PM fro m WRITE GREAT CODE V ol um e 2 : T hi nk in g Low -Lev el , W r i t in g Hi gh -Lev el

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Source URL: tptp.cc

Language: English - Date: 2013-08-27 07:52:46
22Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture

Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture

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Source URL: www.cs.bu.edu

Language: English - Date: 2005-03-23 22:57:42
23Cadastre as pivotal key register in national and European eGovernement Martin Salzmann Cadastre, Land Registry and Mapping

Cadastre as pivotal key register in national and European eGovernement Martin Salzmann Cadastre, Land Registry and Mapping

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Source URL: en.foldhivatal.hu

Language: English - Date: 2011-06-14 14:16:30
24Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12 ,Leonid Oliker12 , John Shalf1 , Samuel Williams12 ,Katherine Yelick12 1  CRD/NERSC, Lawrence Berkeley National Laboratory Ber

Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12 ,Leonid Oliker12 , John Shalf1 , Samuel Williams12 ,Katherine Yelick12 1 CRD/NERSC, Lawrence Berkeley National Laboratory Ber

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Source URL: crd.lbl.gov

Language: English - Date: 2012-09-06 23:57:27
25CS:APP2e Web Aside ASM:SSE: SSE-Based Support for Floating Point∗ Randal E. Bryant David R. O’Hallaron August 5, 2014

CS:APP2e Web Aside ASM:SSE: SSE-Based Support for Floating Point∗ Randal E. Bryant David R. O’Hallaron August 5, 2014

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Source URL: csapp.cs.cmu.edu

Language: English - Date: 2014-08-05 12:50:10
26Symbolic Crosschecking of Floating-Point and SIMD Code Peter Collingbourne Cristian Cadar  Paul H. J. Kelly

Symbolic Crosschecking of Floating-Point and SIMD Code Peter Collingbourne Cristian Cadar Paul H. J. Kelly

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Source URL: www.doc.ic.ac.uk

Language: English - Date: 2016-03-08 07:04:45
27A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation Nuno Roma and Leonel Sousa Instituto Superior Técnico / INESC-ID, Lisboa, Portugal  Abstract:

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation Nuno Roma and Leonel Sousa Instituto Superior Técnico / INESC-ID, Lisboa, Portugal Abstract:

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Source URL: www.inesc-id.pt

Language: English - Date: 2005-11-28 09:18:28
28MIPS Assembly Language Programmer’s Guide ASM-01-DOC  Your comments on our products and publications

MIPS Assembly Language Programmer’s Guide ASM-01-DOC Your comments on our products and publications

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Source URL: www.tik.ee.ethz.ch

Language: English - Date: 2009-09-02 12:08:50
29Analysis of Cross-layer Vulnerability to Variations: An Adaptive Instruction-level to Task-level Approach 1 Abbas Rahimi CSE, UC San Diego La Jolla, CA 92093, USA

Analysis of Cross-layer Vulnerability to Variations: An Adaptive Instruction-level to Task-level Approach 1 Abbas Rahimi CSE, UC San Diego La Jolla, CA 92093, USA

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Source URL: mesl.ucsd.edu

Language: English - Date: 2014-02-11 01:12:49
30CS:APP2e Guide to Y86 Processor Simulators∗  Write back  Stat

CS:APP2e Guide to Y86 Processor Simulators∗ Write back Stat

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Source URL: csapp.cs.cmu.edu

Language: English - Date: 2013-07-29 12:14:16